Seligman, Erik <br/><br/>
Formal verification :   an essential toolkit for modern VLSI design / 
Erik Seligman, Tom Schubert and M V Achutha Kiran Kumar  
 - Amsterdam :  Elsevier,   2015. 
 - xvii, 353 pages :  Illistrations ;  24 cm. 
<br/><br/>Includes index 
<br/><br/><label>ISBN: </label>9780128007273 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electronic  circuits --Testing<br/>Integrated circuits   --very large scale integration--Design and construction.<br/>Verilog (Computer hardware description language)
<br/><br/><label>LC Class. No.: </label>TK 7874.75  /  SEL 2015